Programmable vias for structured ASICs
US8339844B2 · kind B2 · utility
2Cited by
2References
15Claims
0Family size
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Key dates
| Filing date | Mar 12, 2008 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Jul 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/10
Abstract
A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.