Patent · US Active

System and method to access a portion of a level two memory and a level one memory

US8341353B2 · kind B2 · utility

14Cited by

12References

27Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Suresh K. Venkumahanti · Austin, US
Christopher Edward Koob · Round Rock, US
Lucian Codrescu · Austin, US

Key dates

Filing date	Jan 14, 2010
Grant date	Dec 25, 2012
Priority date	—
Expiry date	Sep 10, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0884
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system and method to access data from a portion of a level two memory or from a level one memory is disclosed. In a particular embodiment, the system includes a level one cache and a level two memory. A first portion of the level two memory is coupled to an input port and is addressable in parallel with the level one cache.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.