Single instruction multiple data (SIMD) code generation for parallel loops using versioning and scheduling
US8341615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2008 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Oct 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/456
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention address deficiencies of the art in respect to loop parallelization for a target architecture implementing a shared memory model and provide a novel and non-obvious method, system and computer program product for SIMD code generation for parallel loops using versioning and scheduling. In an embodiment of the invention, within a code compilation data processing system a parallel SIMD loop code generation method can include identifying a loop in a representation of source code as a parallel loop candidate, either through a user directive or through auto-parallelization. The method also can include selecting a trip count condition responsive to a scheduling policy set for the code compilation data processing system and also on a minimal simdizable threshold, determining a trip count and an alignment constraint for the selected loop, and generating a version of a parallel loop in the source code according to the alignment constraint and a comparison of the trip count to the trip count condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.