Vertical-type semiconductor device
US8344385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2010 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Mar 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/27
Abstract
In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns. A plurality of control gate patterns is provided on the blocking dielectric layer between the insulation interlayer patterns. An upper electrode layer pattern is provided on the tunnel oxide layer and …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.