Patent · US Active

Compact memory arrays

US8344429B2 · kind B2 · utility

7Cited by

10References

4Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Jan Otterstedt · Unterhaching, DE
Thomas Nirschl · Putzbrunn, DE
Michael Bollu · Munich, DE
Wolf Allers · Munich, DE

Key dates

Filing date	Sep 17, 2008
Grant date	Jan 1, 2013
Priority date	—
Expiry date	Nov 29, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH10B51/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.