Posting weakly ordered transactions
US8347035B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2008 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Jan 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.