Method and apparatus for addressing and improving holds in logic networks
US8347250B2 · kind B2 · utility
5Cited by
7References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 22, 2010 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Mar 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for modifying a synchronous logic network so that the hold slack calculated at all pins is greater than or equal to a user-specified threshold, with the condition that the setup slack at any pin does not become negative or smaller than a user-specified margin. The result is an improved design which is less likely to fail due to a hold time violation. The method and apparatus introduce a limited number of logic cells which helps keep power consumption and design size to a minimum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.