High-k metal gate CMOS patterning method
US8349680B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2009 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Aug 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02362
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.