System and method for data read of a synchronous serial interface NAND
US8352833B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2012 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Jan 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.