Apparatus and associated method for making a floating gate cell with increased overlay between the control gate and floating gate
US8354335B2 · kind B2 · utility
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2References
19Claims
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Key dates
| Filing date | Dec 22, 2010 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Dec 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.