Patent · US Active

Scheme for varying packing and linking in graphics systems

US8355028B2 · kind B2 · utility

4Cited by

11References

37Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Guofang Jiao · San Diego, US
Alexei V. Bourd · San Diego, US
Chun Yu · San Diego, US
Lingjun Chen · San Diego, US
Yun Du · San Diego, US

Key dates

Filing date	Jul 30, 2007
Grant date	Jan 15, 2013
Priority date	—
Expiry date	Nov 13, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06T15/005
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.