Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

US8357573B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Stephan Kronholz · Dresden, DE
• Markus Lenski · Dresden, DE
• Vassilios Papageorgiou · Austin, US

Key dates

• Filing date: May 3, 2010
• Grant date: Jan 22, 2013
• Expiry date: Dec 16, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.