Method for fabricating buried gate using pre landing plugs
US8357600B2 · kind B2 · utility
4Cited by
2References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2009 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | Feb 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.