Using LPDDR1 bus as transport layer to communicate to flash
US8359423B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2008 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | Jul 8, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention relates to a method for communicating NOR-type flash specific memory commands from a DRAM memory controller to a NOR-type flash memory array without disrupting DRAM operation. In this embodiment flash specific commands are channeled from the DRAM controller to the flash device by using the DRAM protocol as a transport layer. Data to be written to the NOR-type flash memory array are loaded into a data register and a sequence of programming commands are loaded into a mode register as a series of mode register write operations. Once the entire sequence of programming commands is loaded the NOR-type flash memory array the data in the data register is loaded into the NOR-type flash memory array. Other methods and circuits are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.