Stressed channel FET with source/drain buffers

US8361847B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jeffrey B. Johnson · Hague, US
• Ramachandran Muralidhar · Austin, US
• Philip J. Oldiges · Lagrangeville, US
• Viorel Ontalus · Danbury, US
• Kai Xiu · White Plains, US

Key dates

• Filing date: Jan 19, 2011
• Grant date: Jan 29, 2013
• Expiry date: Jan 19, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822

Abstract

A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.