Kai Xiu
8Patents
4h-index
17Co-inventors
46Inventor score
Filing activity: Jul 1, 2005 → Jan 28, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7525162B2 | Orientation-optimized PFETS in CMOS devices employing dual stress liners | Electricity | 15 | Active |
| US8361847B2 | Stressed channel FET with source/drain buffers | Electricity | 14 | Active |
| US7436044B2 | Electrical fuses comprising thin film transistors (TFTS), and methods for programming same | Electricity | 5 | Active |
| US8089160B2 | IC interconnect for high current | Electricity | 4 | Active |
| US7977712B2 | Asymmetric source and drain field effect structure | Electricity | 4 | Active |
| US7342294B2 | SOI bipolar transistors with reduced self heating | Electricity | 3 | Expired |
| US7375371B2 | Structure and method for thermally stressing or testing a semiconductor device | Physics | 3 | Active |
| US8921939B2 | Stressed channel FET with source/drain buffers | Electricity | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.