Method of fabricating semiconductor device
US8361849B2 · kind B2 · utility
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Key dates
| Filing date | Jul 15, 2011 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Jul 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/42
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.