Memory cells, arrays of memory cells, and methods of forming memory cells

US8361856B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Lars Heineck · Dresden, DE
• Jaydip Guha · Boise, US

Key dates

• Filing date: Nov 1, 2010
• Grant date: Jan 29, 2013
• Expiry date: Nov 26, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/485

Abstract

A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions. The inner source/drain region has opposing laterally outer sides. One of a pair of data/sense lines is electrically coupled to and against one of the outer sides of the inner source/drain region. The other of the pair of data/sense lines is electrically coupled to and against the other of the outer sides of the inner source/drain region. An access gate line is elevationally outward of the pair of electrically coupled data/sense lines and is operatively adjacent the channel region. A charge storage device is electrically coupled to the outer source/drain region. Other embodiments and additional aspects, including methods, are disclosed.