Static random access memory (SRAM) write assist circuit with leakage suppression and level control
US8363453B2 · kind B2 · utility
37Cited by
10References
20Claims
0Family size
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Key dates
| Filing date | Dec 3, 2010 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Feb 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) write assist circuit with leakage suppression and level control is described. In one embodiment, the SRAM write assist circuit increases the amount of boost provided in a write cycle, while in another embodiment, the SRAM write assist circuit limits the amount of boost provided at higher supply voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.