Memory device with error correction based on automatic logic inversion
US8365044B2 · kind B2 · utility
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28References
21Claims
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Key dates
| Filing date | Apr 23, 2007 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Feb 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises a memory array and error correction circuitry coupled to the memory array. The error correction circuitry is configured to identify, in a data word retrieved from the memory array, at least one bit position corresponding to a predetermined defect location in the memory array, and to generate a corrected data word by automatically inverting a logic value at the identified bit position. This automatic logic inversion approach is particularly well suited for use in correcting output data errors associated with via defects and weak bit defects in high-density ROM devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.