Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices
US8367471B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 2007 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Mar 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releasably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.