Method to reduce trench capacitor leakage for random access memory device
US8367497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Apr 6, 2028 |
Classification
- Technology area (CPC —)General
Abstract
A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.