Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current
US8368127B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2009 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Jun 14, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/402
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method (and semiconductor device) of fabricating a TFET device provides a source region having at least a portion thereof positioned underneath a gate dielectric. In one embodiment, the TFET includes an N+ drain region and a P+ source region in a silicon substrate, where the N+ drain region is silicon and the P+ source region is silicon germanium (SiGe). The source region includes a first region of a first type (e.g., P+ SiGe) and a second region of a second type (undoped SiGe), where at least a portion of the source region is positioned below the gate dielectric. This structure decreases the tunneling barrier width and increases drive current (Id).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.