Erase operations and apparatus for a memory device
US8369158B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2009 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Jul 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Erase operations and apparatus configured to perform the erase operations are suitable for non-volatile memory devices having memory cells arranged in strings. One such method includes biasing select gate control lines of a string of memory cells to a first bias potential, biasing access lines of a pair of the memory cells to a second bias potential and biasing access lines of one or more remaining memory cells to a third potential. A ramping bias potential is applied to channel regions of the string of memory cells substantially concurrently with or subsequent to biasing the select gate control lines and the access lines, and floating the select gate control lines in response to the ramping bias potential reaching a release bias potential between an initial bias potential of the ramping bias potential and a target bias potential of the ramping bias potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.