Memory word line boost using thin dielectric capacitor
US8369180B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2010 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Apr 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a word line and a word line boost circuit. The word line boost circuit includes a capacitor having a capacitor dielectric thickness, and a transmission gate coupled to the word line and the capacitor. The transmission gate has a gate-dielectric thickness that is greater than the capacitor dielectric thickness. The word line boost circuit is configured to supply a high voltage that is higher than a power supply voltage to the word line during an operation of the memory by utilizing the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.