Patent · US Active

Electronic computing circuit for operand width reduction for a modulo adder followed by saturation concurrent message processing

US8370409B2 · kind B2 · utility

0Cited by

1References

7Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Tobias Gemmeke · Santa Clara, US
Nicolas Maeding · Holzgerlingen, DE
Jochen Preiss · Eppelheim, DE

Key dates

Filing date	Feb 11, 2008
Grant date	Feb 5, 2013
Priority date	—
Expiry date	Dec 8, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F7/499
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A′, B′) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to M bits performed on said two M-bit output operands (A′, B′) provides an M-bit result equal to an M-bit result of an N-bit modulo adder function of the two N-bit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit (1, 5) is described performing said method. Additionally a computer system comprising such an electronic computing circuit is described.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.