Integrated circuit packaging system with stack interconnect and method of manufacture thereof
US8372695B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2010 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Nov 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a substrate base side and a substrate stack side; mounting an integrated circuit over the substrate stack side; attaching a stack connector to the substrate stack side; forming an encapsulation over the stack connector and the integrated circuit; attaching an external connector to the substrate base side; attaching an adhesive tape to the external connector having spacing between the adhesive tape and the substrate base side; cutting a step portion in the encapsulation to expose the stack connector; cutting a singulation kerf in the package substrate having exit damage on the substrate base side; and removing the adhesive tape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.