Gate dielectric first replacement gate processes and integrated circuits therefrom

US8372703B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Brian K. Kirkpatrick · Allen, US
• Freidoon Mehrad · Plano, US
• Shaofeng Yu · Plano, US

Key dates

• Filing date: Oct 20, 2010
• Grant date: Feb 12, 2013
• Expiry date: Dec 28, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/685

Abstract

A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.