Delay lock loop and delay lock method
US8373462B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2011 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Aug 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay lock loop comprising: a first delay loop, for delaying an input signal to generate a first output signal; a second delay loop, for frequency-dividing and delaying the input signal to generate a second output signal, wherein a frequency of the first output signal is higher than which of the second output signal; a phase detector, selectively detecting phases of the input signal, and one of the first delayed output signal and the second delayed output signal, to generate a phase detecting result; and a delay control circuit, for generating a first and a second delay control signal according to the phase detecting result, wherein the first and the second delay control signals are respectively transmitted to the first delay loop and the second delay loop, to control delay amounts of the first delay loop and the second delay loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.