Semiconductor device and delay locked loop circuit thereof
US8373478B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2011 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Dec 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first phase detector for detecting a phase of a second clock by comparing the phase of the second clock with the phase of the first clock, a second phase detector for detecting a phase of a clock obtained by delaying the second clock by a set delay amount, a third phase detector for detecting the phase of the second clock by delaying the first clock by the set delay amount, and a phase difference detection signal generator for setting a logic level of a phase difference detection signal corresponding to a phase difference between the first and second clocks detecting that the phase of the first or second clock is changed, and change the logic level of the phase difference detection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.