Cut first methodology for double exposure double etch integration
US8377795B2 · kind B2 · utility
11Cited by
2References
13Claims
0Family size
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Key dates
| Filing date | Feb 2, 2010 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Oct 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multiple etch process for forming a gate in a semiconductor structure in which a cut area is first formed followed by the forming of the gate conductor lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.