Patent · US Active

III-V semiconductor structures and methods for forming the same

US8377802B2 · kind B2 · utility

3Cited by

1References

13Claims

0Family size

Assignee

SOITEC · FR

Inventors

Ed Lindow · Scottsdale, US
Chantal Arena · Mesa, US
Ronald Thomas Bertram, JR. · Mesa, US
Ranjan Datta · Bengaluru, IN
Subhash Mahajan · Tempe, US

Key dates

Filing date	Mar 23, 2011
Grant date	Feb 19, 2013
Priority date	—
Expiry date	Mar 23, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/0262
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.