Manufacturing method of a semiconductor load board
US8377815B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2011 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Apr 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a semiconductor load board is disclosed. The manufacturing method includes a first conductive layer forming step, a first patterning step, a dielectric layer forming step, a drilling step, a second conductive layer forming step, a second patterning step or a two-times patterning step, and a solder connecting step. In a second patterning step or a two-times patterning step, a solder pad is formed in the opening of the dielectric layer, wherein each solder pad has a height higher than the height of the dielectric, and the width of each solder pad is equal to or smaller than the maximum width of the opening, such that wider intervals are provided in the same area and the problems of short circuit failure and electrical interference can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.