Semiconductor chip bump connection apparatus and method
US8378471B2 · kind B2 · utility
1Cited by
8References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2010 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Jun 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.