Integrated circuit packaging system with stacking option and method of manufacture thereof
US8378476B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2010 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Sep 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate having a component side and a system side; coupling a first integrated circuit die on the component side; coupling stacking interconnects on the component side around the first integrated circuit die; forming a package body on the component side, the first integrated circuit die, and the stacking interconnects; forming vertical insertion cavities through the package body and on the stacking interconnects; and forming a trench, in the package body, adjacent to the vertical insertion cavities for reducing a package warping stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.