Detection of broken word-lines in memory arrays
US8379454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2011 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Jun 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. An “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. The number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.