Semiconductor layer structure and method for fabricating a semiconductor layer structure

US8383495B2 · kind B2 · utility

Assignee

• Siltronic AG · DE

Inventors

• Brian Murphy · Pfarrkirchen, DE
• Maik Haeberlen · Burghausen, DE
• Joerg Lindner · Himmelpforten, DE
• Bernd Stritzker · Kissing, DE

Key dates

• Filing date: Mar 2, 2011
• Grant date: Feb 26, 2013
• Expiry date: Apr 26, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/02551
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.