Tunneling transistor suitable for low voltage operation
US8384122B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2009 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Nov 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/311
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.