Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling

US8384148B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Paolo Tessariol · Montebelluna, IT
• Roberto Bez · Milano, IT
• Marcello Mariani · Milano, IT

Key dates

• Filing date: Dec 22, 2005
• Grant date: Feb 26, 2013
• Expiry date: Nov 21, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A method of making a non-volatile MOS semiconductor memory device includes a formation step, in a semiconductor material substrate, of STI isolation regions (shallow trench isolation) filled by field oxide and of memory cells separated each other by said STI isolation regions. The memory cells include a gate electrode electrically isolated from said semiconductor material substrate by a first dielectric layer, and the gate electrode includes a floating gate self-aligned to the STI isolation regions. The method includes a formation phase of said floating gate exhibiting a substantially saddle shape including a concavity; the formation step of said floating gate includes a deposition step of a first conformal conductor material layer.