Mitigating the effect of single event transients on input/output pins of an integrated circuit device
US8384418B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2011 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Apr 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/007
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for protecting an input/output (I/O) pin of an integrated circuit device (IC) from single event transients is disclosed. The system includes a first delay circuit that is configured to delay a clock signal from the clock source by a first predetermined amount of time, and a second delay circuit that is configured to delay the clock signal by a second predetermined amount of time. The system further includes a first register that is clocked by the clock signal, a second register that is clocked by the clock signal delayed by the first predetermined amount of time, and a third register that is clocked by the clock signal delayed by the second predetermined amount of time. The system also includes voter circuits, where each voter circuit is configured to receive a first data signal from an output of the first register, a second data signal from an output of the second register, and a third data signal from an output of the third register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.