Memory elements having shared selection signals
US8385140B2 · kind B2 · utility
1Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2010 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Apr 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus are provided for memory elements and related computing modules. An exemplary memory element includes a first array of one or more memory cells, a second array of one or more memory cells, write selection circuitry associated with the first array, and read selection circuitry associated with the second array. The write selection circuitry and the read selection circuitry are configured to be activated concurrently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.