Structure for supporting simultaneous storage of trace and standard cache lines
US8386712B2 · kind B2 · utility
3Cited by
53References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 2008 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Oct 28, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.