I/O memory management unit including multilevel address translation for I/O and computation offload
US8386745B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2009 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Aug 8, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/151
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input/output memory management unit (IOMMU) configured to control requests by an I/O device to a system memory includes control logic that may perform a two-level guest translation to translate an address associated with an I/O device-generated request using translation data stored in the system memory. The translation data includes a device table having a number of entries. The control logic may select the device table entry for a given request by the using a device identifier that corresponds to the I/O device that generates the request. The translation data may also include a first set of I/O page tables including a set of guest page tables and a set of nested page tables. The selected device table entry for the given request may include a pointer to the set of guest translation tables, and a last guest translation table includes a pointer to the set of nested page tables.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.