Localized spacer for a multi-gate transistor
US8390040B2 · kind B2 · utility
7Cited by
0References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2009 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Jan 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
Abstract
In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of portions extending onto respective first and second portions of the silicon fin to each act as a self-aligned spacer structure. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.