Non-volatile semiconductor memory device with intrinsic charge trapping layer
US8390056B2 · kind B2 · utility
2Cited by
7References
6Claims
0Family size
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Key dates
| Filing date | Oct 5, 2011 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Oct 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.