ULSI micro-interconnect member having ruthenium electroplating layer on barrier layer
US8390123B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Jan 8, 2009 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Jan 7, 2030 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC25D3/50
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A ULSI micro-interconnect member having a substrate and a ULSI micro-interconnect formed on the substrate, wherein the ULSI micro-interconnect includes a barrier layer formed on the substrate and a ruthenium electroplating layer formed on the barrier layer; the ULSI micro-interconnect member further including a copper electroplating layer formed using the ruthenium electroplating layer as a seed layer; and a process for fabricating the ULSI micro-interconnect members.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.