Coherent instruction cache utilizing cache-op execution resources
US8392663B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2008 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Oct 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor system maintains cache coherence among processors in a coherent domain. Within the coherent domain, a first processor can receive a command to perform a cache maintenance operation. The first processor can determine whether the cache maintenance operation is a coherent operation. For coherent operations, the first processor sends a coherent request message for distribution to other processors in the coherent domain and can cancel execution of the cache maintenance operation pending receipt of intervention messages corresponding to the coherent request. The intervention messages can reflect a global ordering of coherence traffic in the multiprocessor system and can include instructions for maintaining a data cache and an instruction cache of the first processor. Cache maintenance operations that are determined to be non-coherent can be executed at the first processor without sending the coherent request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.