Patent · US Active

Fast REP STOS using grabline operations

US8392693B2 · kind B2 · utility

13Cited by

3References

34Claims

0Family size

Assignee

VIA Technologies, Inc. · TW

Inventors

G. Glenn Henry · Austin, US
Colin Eddy · Austin, US
Rodney E. Hooker · Austin, US

Key dates

Filing date	May 17, 2010
Grant date	Mar 5, 2013
Priority date	—
Expiry date	Nov 10, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/3865
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A microprocessor includes a cache memory and a grabline instruction. The grabline instruction specifies a memory address that implicates a cache line of the memory. The grabline instruction instructs the microprocessor to initiate a zero-beat read-invalidate transaction on the bus to obtain ownership of the cache line. The microprocessor foregoes initiating the transaction on the bus when executing the grabline instruction if the microprocessor determines that a store to the cache line would cause an exception.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.