Method and apparatus for processing load instructions in a microprocessor having an enhanced instruction decoder and an enhanced load store unit
US8392757B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2010 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Aug 3, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and microprocessor are described for efficiently executing load instructions out-of-order (speculatively). The microprocessor includes an enhanced load store unit (LSU) and an enhanced instruction decoder. The enhanced LSU receives a plurality of out-of-order value addresses, and sends a resync signal to the enhanced instruction decoder when an execution error associated with a particular load instruction occurs. The enhanced instruction decoder stores a specific address associated with the particular load instruction, and increments a counter value that indicates how many times the resync signal was sent by the resync predictor. When the counter value reaches a predetermined threshold, subsequent load instructions from the specific address are executed in order (non-speculatively). When a future execution of the particular load instruction indicates that the probability of an execution error has been reduced, the counter value is decremented, facilitating newer load instructions associated with the same address to again be executed speculatively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.