Two-chip co-design and co-optimization in three-dimensional integrated circuit net assignment
US8392870B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2011 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Feb 1, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating optimized input/output (IO) pair and inter-chip connection combinations for two chips is described. In this method, first and second designs for two chips can be specified. Then inter-chip signals based on the first and second designs can be specified. IO pairs for the first and second chips can be determined based on the inter-chip signals. At this point, electrical contacts between micro-bumps (MBs) of the first and second chips can be formed. Inter-chip paths with through-silicon-vias (TSVs) and MBs of the first and second chips can also be formed. At this point, the costs of assigning the IO pairs to the inter-chip paths can be determined. A cost matrix can be built based on these costs. A bipartite matching algorithm can be applied to the cost matrix to determine the optimized IO pair and inter-chip path combinations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.